RISC-V, pronounced “risk five,” is a modern open-source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. In simple terms, it’s like a blueprint that ...
IntroductionOn September 13, 2026, at Hot Chips 2026, Infineon Technologies explained its adoption of RISC-V for automotive processors. What is interesting here is that the company did not position ...
There is great excitement in the world of microprocessors, surrounding the RISC-V architecture. This is an open source modular instruction set specification that has seen implementations on FPGAs, and ...
Advanced Micro Devices (NasdaqGS:AMD) is working with SiFive to tune its open-source ROCm AI software for RISC-V datacenter ...
The AI markets have been relying on data center CPUs based on x86 and ARM architectures for quite some years now. Intel and AMD dominate with x86 offerings, while NVIDIA and other Big Tech companies ...
In a move that’s no doubt going to upset and confuse many, Espressif has released its newest microcontroller — the ESP32-S31. The confusing part here is that the ESP32-S series was always the one ...
Nobody ever thinks of RISC-V when they think of Nvidia, but it's actually incredibly important to Nvidia's GPUs.
Gasgoo Munich- On September 16, at the 2026 6th Smart Automotive Chip Ecosystem Conference hosted by Gasgoo, Liu Lin ...
RISC-V Adoption Accelerates as AI, Edge Computing and Industrial IoT Drive Demand for Customizable, Open-Standard ProcessorsDublin, Sept. 15, 2026 (GLOBE NEWSWIRE) -- "RISC-V Market Opportunity, ...
Earlier this month, Qualcomm announced it was working with Google on a RISC-V Wear OS chip. The Android team today provided an update on RISC-V adoption, including an initial timeline and emulator ...
Forbes contributors publish independent expert analyses and insights. Marco Chiappetta is a technologist who covers semiconductors and AI. In recent years, the RISC-V architecture has gained ...
At The 6th Automotive Semiconductor Ecosystem Conference 2026 on 6, Ding Ke — Senior Deputy Chief Engineer of Chip ...
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